akd8181b pattern a pattern b akd8181 b ak8181 b evaluation board the akd8181 b is an evaluation board for ak8181 b . therefore, it is easy to evaluate dc/ac characteristics and confirm product functions. - sma terminal input - crystal can be mounted - enable to construct three types of output load circuit - preparing terminal and land pattern for vdd/vee - clk_sel and clk_en control switch vdd vee vdd - 2v output pin q0/q0n output pin q1/q1n output pin q2/q2n output pin q3/q3n clk input clk_en clk_sel crystal akd8181b-e-00 1 2012/7
akd8181b pattern a composition at the time of shipment ncno components rtt: 50? is mounted at the time of shipment pattern b power there are the following t hree power supplies. if you have configured a termination circuit with resistor only (pattern a or b), it becomes possible to evaluate even without applying power to the vdd - 2v terminal. - vdd - vee - vdd - 2v clock input ak8181 b inputs the clock selected by clk_sel switch . ( external input or crystal ) the clock input signal can terminate at 50? if needed. (50? is connected to r2 pattern) inputs 266mhz or less. output load circuit it can terminate by the following t hree methods. (pattern a/b /c ) the state of initial shipment is pattern a . the core power supply of ak8181 b (3.3v) the core power supply of ak8181 b (gnd) power supply for the end of the output load resistor (=vdd - 2v) note) gnd of the sma terminal is connected to the vee inside the substrate. q0,1,2,3 q0n,1n, 2n,3n 50 50 nc nc zo=50 zo=50 q0,1,2,3 q0n,1n, 2n,3n 0 0 0.1uf or open rtt 84 84 zo=50 zo=50 0 0 short 125 125 akd8181b-e-00 2 2012/7 ? ? 0 2 ) 2 /( ) ( 1 z v v v rtt cc ol oh ? ? ? ? ? ? ? ? ? ?
akd8181b pattern c please impress a power to vdd-2v terminal. if you have configured a termination circuit with resistor only (pattern a or b), it becomes possible to q0,1,2,3 q0n,1n, 2n,3n nc nc zo=50 zo=50 50 50 vdd - 2v nc nc nc short short akd8181b-e-00 3 2012/7
akd8181b according to the circumstances, please set up the output load circuit of q0/0n, q1/1n, q2/2n and q3/3n. the state of initial shipment is pattern a . refer to the "output load circuit" at page 2. akd8181b-e-00 4 2012/7
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